In recently years, forming in fidelity a fine circuit pattern on a wafer by optical exposure have progressively been difficult with accompanying miniaturization of a semiconductor device.
A correction amount in transferring the circuit pattern in a mask to a surface of the wafer for improvement of the circuit pattern fidelity is preliminarily estimated in the circuit pattern in the mask to be incorporated in the technique mentioned above. The process mentioned above is optical proximity correction which is called OPC hereinafter.
A large amount of time is consumed in verification of forming the mask pattern such as mask verification, lithography verification or the like for improving a device yield which is a ratio of good chips per wafer with companying highly-developed semiconductor production technology. Therefore, a problem in which verification turn around time called verification TAT hereinafter is increased is generated.
An OPC non-adaptation pattern and the correction method, for example, are saved in a library. In the method, a circuit pattern newly input in a verification apparatus is matched with the OPC non-adaptation pattern. In such a manner, verification TAT is intended to be shortened.
Here, the OPC non-adaptation pattern is defined as a circuit pattern estimated to be judged as OPC non-adaptation or a circuit pattern judged as OPC non-adaptation in production verification.
There are infinite kinds of OPC non-adaptation patterns, however, the OPC non-adaptation patterns which can be saved in the library remains finite.
Accordingly, the OPC non-adaptation patterns not to be set in the library may set to be in the circuit patterns input into the verification apparatus.
As a result, whole circuit patterns input into the verification apparatus has a necessity to be again verified. Therefore, verification TAT may be likely not to be shortened.
Further, verification TAT is increased with accompanying enlargement and complexity of circuits in the semiconductor device in recent years.
Accordingly, it is desirable to be realized the mask pattern verification apparatus and the mask pattern verification method which are capable of shorten the verification TAT and a method of fabricating a semiconductor device using the mask pattern verification method.